1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a protective element (electrostatic protective element) for protection against electrostatic discharges (ESD).
2. Description of the Related Art
In recent years, with increased miniaturization of semiconductor devices, there is a greater likelihood that minute levels of electrostatic energy will destroy these devices. Under the circumstances, attention has been drawn to ESD-related technologies for protecting internal circuits that are made up of semiconductor devices.
In order to prevent a large current due to an ESD surge from flowing into an internal circuit, which makes semiconductor devices, connected to pads, it has been customary in the art to protect the internal circuit with ESD protective elements that are disposed near the pads (see JP2011-61232A).
However, the inventors of the present invention have found a problem that, when ESD surges occur successively, electric charges that are caused by the ESD surges tend to be stored in the internal circuit without being released from the internal circuit through the ESD protective elements. The problem will be described in detail below.
According to the product specifications for some semiconductor devices, power supply pads are separate from each other for various reasons including potential differences, noise suppression, etc.
FIG. 1A shows the package of a prototype semiconductor device that the inventors have conceived in the course of making the present invention. In FIG. 1, power supply voltages VDD and VSS, which are used for peripheral circuits, and power supply voltages VDDL and VSSDL, which are used for DLL (Delay Locked Loop) circuits, are separate from each other. The power supply voltage VSS represents a ground potential. Therefore, the ground potential is also referred to as ground potential VSS. The semiconductor device may be a semiconductor storage device including a DRAM.
In FIG. 1A, VDD pad 1011 and VSS pad 1012 are pads for external power supplies used by the peripheral circuits. VDDL pad 1013 and VSSDL pad 1014 are pads for external power supplies that are dedicated to the DLL circuits.
In the semiconductor device shown in FIG. 1A, the power supplies used by the peripheral circuits and the power supplies dedicated to the DLL circuits have identical potentials, but are separate from each other for noise suppression. Therefore, VDD pad 1011 and VDDL pad 1013 are separate from each other, and VSS pad 1012 and VSSDL pad 1014 are separate from each other.
FIG. 1B shows a chip incorporated in the package of the prototype semiconductor device. The chip will be described below with reference to FIG. 1B.
As shown in FIG. 1B, the chip includes VDD pads 101 connected to VDD pad 1011 of the package, VDDL pad 103 connected to VDDL pad 1013 of the package, VSS pads 102 connected to VSS pad 1012 of the package, VSSDL pad 104 connected to VSSDL pad 1014 of the package, DLL circuit area 105 where DLL circuits are located, array areas AR where memory arrays are located, and peripheral circuit areas 106 that control signals input to and output from DQ pads and ADDRESS pads. DLL circuit area 105 where DLL circuits are located is isolated from substrate P-sub by deep N well layer DNW to prevent noise produced in DLL circuit area 105 from being propagated from VSSKL pad 104 via substrate P-sub to VSS pads 102 and to circuits, e.g., peripheral circuits to be described later, connected to VSS pads 102. VDDL pad 103 and VDD pads 101 are disposed independently of each other. Pads which are not particularly denoted in FIGS. 1A and 1B are assigned as DQ pads, ADDRESS pads, and power supply pads other than VDDL and VSSDL pads, and will not be described in detail below as they have no direct bearing on the present invention.
The peripheral circuits, which are connected to VDD pads 101 and VSS pads 102, are located in peripheral circuit areas 106 which are not enclosed by deep N well layer DNW. Only DLL circuits are connected to VDDL pad 103 and VSSDL pad 104. VSS pads 102 are kept at ground potential VSS supplied from a ground electrode. Since VSS pads 102 are connected to substrate P-sub, substrate P-sub is also kept at ground potential VSS.
FIG. 2A shows circuits in the prototype semiconductor device shown in FIGS. 1A and 1B, and FIG. 2B shows the layout of DLL circuit B in the semiconductor device shown in FIG. 2A. ESD protective elements (hereinafter simply referred to as “protective elements”) disposed near pads will be described below with reference to FIGS. 2A and 2B. In FIG. 2B, attention is directed to protective element Al for the sake of brevity, with other protective elements being omitted from illustration.
The semiconductor device includes VDD pad 101, VSS pad 102, VDDL pad 103, VSSDL pad 104, protective elements A1 through A5, DLL circuit B in DLL circuit area 105, peripheral circuit 106A in peripheral circuit area 106, ground electrode T, and interconnects S1 through S8. Ground electrode T is connected by interconnect S8 to VSS pad 102 which supplies the ground potential. DLL circuit B is located in DLL circuit area 105. DLL circuit B is supplied with VDDL, e.g., power supply potential VDD, and VSSL, e.g., ground potential VSS, through interconnect S1 and through interconnect S2. Interconnect S1 is disposed in DLL circuit area 105 and connected to interconnect S3 that interconnects DLL circuit arca 105 and VDDL pad 103. Interconnect S2 is disposed in DLL circuit area 105 and connected to interconnect S4 that interconnects DLL circuit area 105 and VSSDL pad 104.
DLL circuit B is constructed of a plurality of internal circuits, e.g., internal circuits B1 and B2. Internal circuit B1 includes a plurality of PMOS transistors PMOS, a plurality of NMOS transistors NMOS, interconnect S1a functioning as interconnect S1 in internal circuit B1, and interconnect S2a functioning as interconnect S2 in internal circuit B1. Similarly, internal circuit B2 includes a plurality of PMOS transistors PMOS, a plurality of NMOS transistors NMOS, interconnect S1b functioning as interconnect S1 in internal circuit B2, and interconnect S2b functioning as interconnect S2 in internal circuit B2. Interconnect S1 is made up of interconnect S1a and interconnect S1b, and interconnect S2 is made up of interconnect S2a and interconnect S2b. Interconnect S3 interconnects VDDL pad 103 and interconnect S1. Interconnect S4 interconnects VDDL pad 104 and interconnect S2.
Peripheral circuit 106A includes a plurality of PMOS transistors PMOS, a plurality of NMOS transistors NMOS, interconnect S5 for VDD, and interconnect S6 for VSS. Interconnect S7 interconnects VDD pad 101 and interconnect S5. Interconnect S8 interconnects VSS pad 102 and interconnect S6.
Generally, protective elements are disposed near pads and disposed between pads and internal circuits, and comprise a diode-connected transistor.
In FIG. 2A, protective elements that are connected to VDDL pad 103 include protective element A1 and protective element A2. Protective element A1 has a source and a drain which are connected respectively to ground electrode T and VDDL pad 103. Protective element A2 has a source and a drain which are connected respectively to VSSDL pad 104 and VDDL pad 103.
Resistor R1 represents a parasitic resistor from VDDL pad 103 to internal circuit B1. Resistor R2 represents a parasitic resistor from VDDL pad 103 to internal circuit B2. Electric charge Q1 represents an electric charge stored in internal circuit B1. Electric charge Q2 represents an electric charge stored in internal circuit B2.
As shown in FIG. 2B, functional cells C represent circuit units each having a small-scale function. Functional blocks D1 through D4 represent circuits each having a particular function performed by a combination of functional cells C.
Power supply lines CS11, CS21, CS31, CS41, CS51 and CS61 supply adjacent functional cells C with power supply voltage VDDL that is supplied from VDDL pad 103 through interconnect S1. Power supply lines CS12, CS22, CS32, CS42, CS52 and CS62 supply adjacent functional cells C with power supply voltage VSSDL that is supplied from VSSDL pad 104 through interconnect S2.
FIG. 2C shows in cross section DLL circuit B which is isolated by deep N well layer DNW from substrate P-sub that is supplied with potential VSS. Since DLL circuit B is isolated by deep N well layer DNW from substrate P-sub, DLL circuit B is not connected to ground electrode T under potential VSS.
Principles of operation of the protective elements will be described below.
FIG. 3 shows in cross section protective element A1. FIG. 4 shows an Id-Vd characteristic curve of protective element A1. Operation of protective element A1 will be described below with reference to FIGS. 3 and 4. In FIGS. 3 and 4, VSS represents ground potential.
When a voltage is applied to VDDL pad 103 that is connected to drain Drain of protective element A1, drain voltage Vd of protective element A1 increases. When drain voltage Vd reaches voltage Vd0 shown in FIG. 4, a current flows from drain Drain to subcontact E1 through P well layer P-Well. Such a current path will be referred to as path F1 in protective element A1.
Thereafter, the voltage of P well layer P-Well near source Source of protective element A1 rises due to the current flowing through the parasitic resistor in P well layer P-Well. When the voltage between P well layer P-Well and source Source exceeds a certain level, the PN junction between P well layer P-Well and source Source is forward-biased, thereby producing a low-resistance current path from drain Drain to source Source. Such a current path will be referred to as path F2 in protective element A1.
This phenomenon is known as snapback. Voltage Vd1 where snapback occurs is referred to as a trigger voltage.
When snapback occurs in protective element A1, the current from VDDL pad 103 is discharged through path F2 into ground electrode T, thereby reducing the current flowing from VDDL pad 103 into DLL circuit B. Before snapback occurs, the current from VDDL pad 103 also flows into DDL circuit B.
Examples of ESD-applied pulses will be described below.
FIGS. 5A through 5D show typical models of ESD-applied pulses.
FIG. 5A shows package-charged model CDM in which a large current flows at a high speed.
FIG. 5B shows machine model MM in which a current having a medium amplitude flows.
FIG. 5C shows human body model HBM in which a small current flows.
Circuit operation according to the related art, upon application of an HBM pulse, will be described below with reference to FIGS. 6A, 6B, and 7.
FIG. 6A shows an HBM pulse, and FIG. 6B shows currents flowing through current path G1 and through current path G2 shown in FIG. 7.
When the HBM pulse shown in FIG. 6A is applied to VDDL pad 103, currents flow respectively through current path G1 and current path G2. Current path GI corresponds to path F1 shown in FIG. 3.
Since protective element A1 exhibits the Id-Vd characteristic curve shown in FIG. 4, a current flows from VDDL pad 103 through current path G2 into DLL circuit B prior to snapback (before protective operation starting time t1 shown in FIG. 6B).
Thereafter, when the voltage applied to protective element A1 exceeds the trigger voltage, snapback occurs.
When snapback occurs in protective element A1, a current abruptly starts to flow from VDDL 103 through protective element A1 into ground electrode T (after protective operation starting time t1 shown in FIG. 6B).
The current flowing into DLL circuit B is reduced, and the gate voltage of DLL circuit B does not exceed a gate withstand voltage of the DLL circuit B, which is thus prevented from suffering an ESD breakdown.
Storage of an electric charge in DLL circuit B will be described below.
Since Q=I·t, the amount of electric charge stored in DLL circuit B is equal to the area of region H1 shown in FIG. 6B.
A while after the protective operation stating time, the current flowing through current path G2 is drawn to protective element A1, and the direction of the current flowing through current path G2 is reversed (see FIG. 8).
Up to the point immediately before the direction of the current flowing through current path G2 is reversed, the electric charge is continuously stored in DLL circuit B, and the amount of the electric charge stored in DLL circuit B at this time is represented by the area of region H1 shown in FIG. 6B.
The reversal of the direction of the current flowing through current path G2 means that DLL circuit B is discharged. After DLL circuit discharge starting time t2 in FIG. 6B, the electric charges stored in DLL circuit B are discharged through protective element A1 into ground electrode T until finally they become nil.
At this time, the amount of electric charge stored in DLL circuit B is equal to the amount of electric charge discharged from DLL circuit B.
Problems with respect to the connection of protective elements according to the related art will be described below.
Actual semiconductor devices may not be subjected to a single pulse applied thereto as shown in FIG. 5A, 5B, or 5C, but to a succession of pulses applied thereto as shown in FIG. 9A, for example.
If a protective element is connected to a semiconductor device according to the related art, then the semiconductor device tends to suffer an ESD breakdown due to such a succession of pulses applied thereto. The mechanism of such an ESD breakdown will be described below.
When pulse I1 shown in FIG. 9A is applied to VDDL pad 103, an electric charge is initially stored in DLL circuit B by pulse I1, and is thereafter discharged through protective element A1 into ground electrode T.
When a succession of pulses shown in FIG. 9A is applied to VDDL pad 103, an electric charge is stored in DLL circuit B by the respective pulses and then discharged as shown in FIG. 9B. At this time, however, while an electric charge stored in DLL circuit B by each pulse is being discharged, a next pulse is applied to VDDL pad 103. For example, when pulse 12 is applied to VDDL pad 103, an electric charge stored in DDL circuit B by pulse I1 still remains undischarged.
Consequently, as shown in FIG. 9B, the amount of electric charge stored in DDL circuit B by pulse 12 in the duration thereof becomes greater than the amount of electric charge stored in DDL circuit B by pulse I1 in the duration thereof.
A path along which the electric charge stored in DDL circuit B is discharged will be described below with reference to FIG. 10.
In FIG. 10, the distance along the interconnect from VDDL pad 103 to interconnect S1b in internal circuit B2 is greater than the distance along the interconnect from VDDL pad 103 to interconnect S1a in internal circuit B1. Therefore, the resistance of resistor R2 is greater than the resistance of resistor R1.
The path along which electric charge Q1 stored in internal circuit B1 is referred to as discharge path J1, and the path along which electric charge Q2 stored in internal circuit B2 is referred to as discharge path J2.
Since the resistance of resistor R2 is greater than the resistance of resistor R1, electric charge Q1 is discharged more easily through discharge path J1 than electric charge Q2 is discharged through discharge path J2.
Therefore, the “electric charge that remains undischarged in the duration of pulse I1” in FIG. 9B is mostly the electric charge that is stored in internal circuit B2 at the time pulse 12 starts to be applied.
When a succession of ESD-induced pulses is applied to VDDL pad 103, the amount of electric charge stored in internal circuit B2, which is remotest from VDDL pad 103 among the connected internal circuits, progressively grows until finally the gate of internal circuit B is destroyed.